Such devices are widely used in the art. They are based on well known error detection algorithms such as the Cyclic Redundancy Check (CRC) algorithm which detect the bit position of an erroneous bit. Since a bit can only have two values, i.e. 0 or 1, correction of an erroneous bit is obvious when its position is known.
This algorithm and other error check techniques are for example described in chapter 5 of the book "Digital Communications-Fundamentals and Applications" by Bernard Sklar, published by Prentice-Hall International Editions, 1988.
The known devices mostly rely on the fact that the sequence of bits to be processed is received serially or can easily be converted to a serial bit stream.
However, in case of parallel processing of the bits, e.g. on a parallel bus to increase the transmission speed of the bits, their design becomes complicated since application of the algorithm then requires storage and rearrangement of the received bits or of received sets of bits, mostly bytes. The design of these devices becomes even more complicated when the transmitted bits do not use all bit positions on the bus. For example in case of bits transmitted in bytes over a 2 byte bus, a first byte of the sequence can start at a first or a second byte position of the bus. This start position has then to be known by the device in order to know how many bits or bytes have to be processed. Moreover, when the sequence contains an odd number of bytes, this start position alters, thereby additionally complicating the design of the device.